In semiconductor processes, tilted ion implantation is often carried out. For example, in forming source/drain regions for CMOS devices by the ion implantation process, generally the ion implantation is performed in a tilt angle, to form shallow junctions so as to avoid the tunneling effect. Further, in manufacturing short channel devices, generally halo implantation is performed in a relatively large tilt angle, to suppress short channel effects.
However, the tilted ion implantation may cause implanted ions pass through a gate dielectric layer, and thus cause damages on the gate dielectric layer. As a result, a resulting device may become failed due to sharp increase of the gate leakage current. This problem becomes particularly serious when implanting large-sized impurity ions, such as P, Ge, and As, in a great dose with a high energy.
One conventional solution to the problem is to deposit a dielectric spacer (e.g., silicon oxide or silicon nitride) on side walls of a gate stack prior to the ion implantation process, to alleviate the damages on the gate dielectric layer caused by the implanted ions. However, it is impossible to completely eliminate the damages on the gate dielectric layer with this solution. As a result, the resulting device has its performances degraded to some extent.